In order to improve data reading and writing speeds, there is known a technique for precharging bit lines connected to a memory cell before accessing the memory cell.
FIG. 1 is a diagram illustrating a configuration of a conventional SRAM. Referring to FIG. 1, the conventional SRAM includes a plurality of memory cells (SRAM cells) 100 respectively connected to a plurality of word lines WL0 to WLi and a plurality of pairs of bit lines BL0 and /BL0 to BLj and /BLj. A precharge circuit 110 is connected between a power supply voltage Vcc and the plurality of pairs of bit lines BL0 and /BL0 to BLj and /BLj. The plurality of pairs of bit lines BL0 and /BL0 to BLj and /BLj are connected to a sense amplifier 13 and a write driver 14 through a bit line selecting section of bit line selection transistors MN11, MN12, MP16, and MP17 for each pair of bit lines. The precharge circuit 110 precharges the plurality of pairs of bit lines with the power supply voltage Vcc in response to a precharge control signal PC from a precharge (PC) driver 120. Specifically, the precharge circuit 110 is provided with precharge transistors MP23 and MP24 and equalizing transistor MP25 for each pair of bit lines and these transistors are controlled in response to the precharge control signal PC supplied to gates of the respective transistors. The precharge transistors MP23 and MP24 are P-channel MOS transistors that control a connection between the power supply voltage Vcc and each pair of bit lines in response to the precharge control signal PC. The equalizing transistor MP25 is a P-channel MOS transistor and controls a connection between the bit lines of each pair in response to the precharge control signal PC.
FIG. 2 shows timing charts in a data read operation on the memory cell of the conventional SRAM. Referring to FIG. 2, the data read operation on the memory cell 100 connected to the bit line pair BL0 and /BL0 and the word line WL0 will be described. Before the word line WL0 is activated, the precharge driver 120 outputs the precharge control signal PC in a low level to the precharge circuit 110. In response to the precharge control signal PC, the precharge circuit 110 supplies a precharge voltage of the power supply voltage Vcc (1.0 V in this case) to the pair of bit lines BL0 and /BL0, and also equalizes the pair of bit lines BL0 and /BL0. That is, before the activation of the word line WL0, the pair of bit lines BL0 and /BL0 are precharged to the power supply voltage Vcc (1.0 V).
When the word line WL0 is to be selected, the precharge driver 120 starts to increase a signal level of the precharge control signal PC prior to the activation of the word line WL0 (time T1). In response to the precharge control signal PC having the high level, the precharge circuit 110 sets the pair of bit lines BL0 and /BL0 into a floating state by disconnecting the power supply voltage Vcc from the pair of bit lines BL0 and/BL0. Then, the word line WL0 is activated by a word line driver (not shown) (time T2). While the word line WL0 is in an activation state, voltages on the pair of bit lines BL0 and /BL0 are detected by the sense amplifier 13 (time T3).
It is assumed that, in the memory cell 100, the bit line BL0 is connected to a node in the low level, and the bit line /BL0 is connected to a node in the high level. In this case, when the word line WL0 is activated, the voltage of the bit line BL0 reduces and a difference between the voltage on the bit line BL0 and the voltage (the power supply voltage Vcc) on the bit line /BL0 is sensed by the sense amplifier 13. Thus, a data having stored in the memory cell 100 can be determined. As described above, the data having stored in the memory cell 100 which is connected to the word line WL0 and the pair of bit lines BL0 and /BL0 is read.
After the data has been read, the word line WL0 is deactivated (time T4), and then the precharge driver 120 starts to decrease the signal level of the precharge control signal PC to the low level (time T5). In response to the precharge control signal PC in the low level, the precharge circuit 110 connects the power supply voltage Vcc and each pair of bit lines, and also equalizes the bit lines of each pair. Thus, each pair of bit lines is precharged to the power supply voltage Vcc (1.0 V). At this time, due to the equalizing operation at the time T5, the voltage on the bit line /BL0 connected to the node in the high level data is temporarily reduced, but then precharged to the power supply voltage Vcc with time.
FIG. 3 shows timing charts in a data write operation on the memory cell of the conventional SRAM. Referring to FIG. 3, the data write operation on the memory cell 100 connected to the pair of bit lines BL0 and /BL0 and the word line WL0 will be described. Before the word line WL0 is activated, the precharge driver 120 outputs the precharge control signal PC in the low level to the precharge circuit 110. In response to the precharge control signal PC in the low level, the precharge circuit 110 supplies the precharge voltage of the power supply voltage Vcc (1.0 V in this case) to each pair of bit lines, and also equalizes the bit lines of each pair. That is, before the activation of the word line WL0, the bit lines BL0 and /BL0 are precharged to the high level (power supply voltage Vcc: 1.0 V).
When the word line WL0 is selected, the precharge driver 120 starts to increase the signal level of the precharge control signal PC prior to the activation of the word line WL0 (time T1). In response to the precharge control signal PC in the high level, the precharge circuit 110 sets each pair of bit lines into the floating state to disconnect each pair of bit lines from the power supply voltage Vcc. Then, the word line WL0 is activated by a word line driver (not shown) (time T2), and a data is written in one memory cell by the write driver 14 (time T3). It is assumed that in the memory cell 100, a bit data in the high level is written to the node connected to the bit line BL0, and a bit data in the low level is written into the node connected to the bit line /BL0. In this case, the bit line BL0 becomes the high level (power supply voltage Vcc: 1.0 V), and the bit line /BL0 becomes the low level (ground voltage GND: 0 V).
After the data has been written, the word line WL0 is deactivated (time T4), and then the precharge driver 120 starts to decrease the signal level of the precharge control signal PC to the low level (time T5). In response to the precharge control signal PC in the low level, the precharge circuit 110 connects the power supply voltage Vcc and each pair of bit lines, and also equalizes the bit lines of each pair. Thus, the bit lines of each pair are precharged to the power supply voltage Vcc (1.0 V). At this time, due to the equalizing operation at the time T5, the voltage on the bit line /BL0 connected to the node in the high level data is temporarily reduced, but then precharged to the power supply voltage Vcc with time.
As described, in the conventional SRAM, before accessing the memory cell (selecting the word line), the pair of bit lines is precharged with the power supply voltage Vcc, and thereby the data reading and writing speeds can be improved.
On the other hand, as a memory characteristic of the conventional SRAM, an SNM (Static Noise Margin) is known. If the SNM is small, a write data is likely to be inverted due to noise received by a bit line. When the precharge voltage is equal to the power supply voltage as in the conventional SRAM illustrated in FIG. 1, the SNM is relatively small, and the write data is likely to be inverted.
In order to avoid such an inversion of data, a technique is known that sets the precharge voltage lower than the power supply voltage, and thereby increases the SNM to prevent data from being inverted due to noise. For example, Japanese Patent Publications (JP 2003-257182A: patent literature 1 and JP 2007-164888A: patent literature 2) describes SRAMs in which a precharge voltage is lower than the power supply voltage.